- Introduction
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Syllabus
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Introduction 1 min
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Ethernet: The Early Years 2 min
- OSI (Open Systems Interconnection) Model
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OSI Model Overview 5 min
- Physical Layer
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The PHY 7 min
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Knowledge Check
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Copper Design Guidelines 5 min
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Copper Signaling Standards 13 min
- Data Link Layer
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Ethernet Packet Structure 2 min
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Media Independent Interface (MII) 4 min
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MII Management Interface 3 min
- Troubleshooting
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Board Bring-Up 5 min
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Systematic Debug Approach 13 min
- Your Feedback
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We need your Feedback
Ethernet Fundamentals
This class will enable an engineer with no prior Ethernet knowledge to successfully design with Ethernet PHYs, controllers, and switches. (Nov 2021)
This class will enable an engineer with no prior Ethernet knowledge to successfully design with Ethernet PHYs, controllers, and switches. The material explained in this class will reduce time to market and board re-spins for 10/100/1000 Mbps Ethernet hardware designs. The functional blocks which make up the physical and MAC layers (layers 1 and 2) will be explained along with the hardware interfaces between those building blocks and your embedded system. Schematic design, board layout, test, and debug will be explained while referencing lessons learned from years of Microchip's Ethernet hardware design.